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=UNL CSCE 830 - Course Project =

Members:
 Vlad Chiriacescu  Sergio Rico  Ertong Zhang  Zhongyin Zhang

Meeting date: Saturday, 11.15 AM
**Meeting 1:**

 1) All of us installed the blaster driver.

 2) Ran a clock example too see the steps that need to be performed in Quartus and  to get used with the board output.

 3) Established the bubble sort algorithm in assembly. Rough ideas about the number  and specific instructions that will form our ISA.

 4) Until the next meeting we try to get through a VHDL tutorial and maybe a little bit  on an assembly language one.

**Update 1:**

<span style="font-family: Arial,Helvetica,sans-serif;"> 1) We figured out how to install the RS232 driver on Windows 7.

<span style="font-family: Arial,Helvetica,sans-serif;">**Meeting 2:**

<span style="font-family: Arial,Helvetica,sans-serif;"> 1) We came up with 3 different versions of the assembler code for bubble sort. <span style="font-family: Arial,Helvetica,sans-serif;"> We compared them and then we chose our ISA.

<span style="font-family: Arial,Helvetica,sans-serif;"> 2) We simulated the execution of a few instructions from the single cycle example.

<span style="font-family: Arial,Helvetica,sans-serif;"> 3) Until the next meeting we will try to implement the assembler needed.

<span style="font-family: Arial,Helvetica,sans-serif;"> 4) Some of us will continue looking at the single cycle example to understand it better <span style="font-family: Arial,Helvetica,sans-serif;"> and even come up with some new parts needed for some of our instructions.

<span style="font-family: Arial,Helvetica,sans-serif;">**Meeting 3:**

<span style="font-family: Arial,Helvetica,sans-serif;"> 1) We came up with an improved version of the single cycle processor. <span style="font-family: Arial,Helvetica,sans-serif;"> 2) We successfully ran the serial communication example.

<span style="font-family: Arial,Helvetica,sans-serif;">**Milestone 2:**

<span style="font-family: Arial,Helvetica,sans-serif;">**1) Instruction set architecture**

<span style="font-family: Arial,Helvetica,sans-serif;"> Decided ISA is composed of the following instruction subset of the MIPS architecture:

<span style="font-family: Arial,Helvetica,sans-serif;"> Add immediate (addi) <span style="font-family: Arial,Helvetica,sans-serif;"> Load word (lw) <span style="font-family: Arial,Helvetica,sans-serif;"> Set on less than (signed) (slt) <span style="font-family: Arial,Helvetica,sans-serif;"> Branch on equal (beq) <span style="font-family: Arial,Helvetica,sans-serif;"> Store word (sw)

<span style="font-family: Arial,Helvetica,sans-serif;"> We also created the instruction called "uart" for communication with the UART RS232 transceiver.

<span style="font-family: Arial,Helvetica,sans-serif;">**2) Test data**

<span style="font-family: Arial,Helvetica,sans-serif;"> The data part of our MIF data file is:

<span style="font-family: Arial,Helvetica,sans-serif;"> [00..FF]: 00000000;

<span style="font-family: Arial,Helvetica,sans-serif;"> 00 : 00000006; <span style="font-family: Arial,Helvetica,sans-serif;"> 01 : 55555555; <span style="font-family: Arial,Helvetica,sans-serif;"> 02 : AAAAAAAA; <span style="font-family: Arial,Helvetica,sans-serif;"> 03 : 00000010; <span style="font-family: Arial,Helvetica,sans-serif;"> 04 : 00000001; <span style="font-family: Arial,Helvetica,sans-serif;"> 05 : F0000000; <span style="font-family: Arial,Helvetica,sans-serif;"> 06 : 12300000;

<span style="font-family: Arial,Helvetica,sans-serif;"> This data has been used as input to the sorting algorithm ran on the processor. <span style="font-family: Arial,Helvetica,sans-serif;"> Verification has been done with ModelSim and also directly on the board.

<span style="font-family: Arial,Helvetica,sans-serif;">**3) Top level design**

<span style="font-family: Arial,Helvetica,sans-serif;"> Entity MIPS with components:

<span style="font-family: Arial,Helvetica,sans-serif;"> Component Ifetch <span style="font-family: Arial,Helvetica,sans-serif;"> Component Idecode <span style="font-family: Arial,Helvetica,sans-serif;"> Component control <span style="font-family: Arial,Helvetica,sans-serif;"> Component execute <span style="font-family: Arial,Helvetica,sans-serif;"> Component dmemory

<span style="font-family: Arial,Helvetica,sans-serif;">**4) Serial communication**

<span style="font-family: Arial,Helvetica,sans-serif;"> In the last days, we managed to integrate the UART example with <span style="font-family: Arial,Helvetica,sans-serif;"> our processor and displayed the result of sorting in the Putty terminal.

<span style="font-family: Arial,Helvetica,sans-serif;">**Milestone 3 - pipelining the processor**

<span style="font-family: Arial,Helvetica,sans-serif;"> 1) For this step we implemented latches between each two processor stages in order to <span style="font-family: Arial,Helvetica,sans-serif;"> realise the pipeline.

<span style="font-family: Arial,Helvetica,sans-serif;"> 2) We added NOPs to the bubble sort algorithm in order to avoid data and control hazards.

<span style="font-family: Arial,Helvetica,sans-serif;"> 3) We modified our assembler program so that it can correctly transform the new <span style="font-family: Arial,Helvetica,sans-serif;"> bubble sort code into the correct MIF file.

<span style="font-family: Arial,Helvetica,sans-serif;"> 4) We successfully simulated the new project using ModelSim.

<span style="font-family: Arial,Helvetica,sans-serif;"> 5) The tests with the board have passed successfully. Here are our latest results, as shown <span style="font-family: Arial,Helvetica,sans-serif;"> in the Putty terminal:

<span style="font-family: Arial,Helvetica,sans-serif;"> AAAAAAAA <span style="font-family: Arial,Helvetica,sans-serif;"> F0000000 <span style="font-family: Arial,Helvetica,sans-serif;"> 00000001 <span style="font-family: Arial,Helvetica,sans-serif;"> 00000010 <span style="font-family: Arial,Helvetica,sans-serif;"> 12300000 <span style="font-family: Arial,Helvetica,sans-serif;"> 55555555

<span style="font-family: Arial,Helvetica,sans-serif;">**Milestone 4 - Data forwarding**

<span style="font-family: Arial,Helvetica,sans-serif;">Before data is sent to the execution (EXE) stage, the ID stage asks the EXE, DM and WB stages <span style="font-family: Arial,Helvetica,sans-serif;">to send their current data. Then in the ID stage, a dependency check is made on the data received <span style="font-family: Arial,Helvetica,sans-serif;">from those other stages. The ID will change the data in the two registers A and B according to the <span style="font-family: Arial,Helvetica,sans-serif;">dependencies found and avoid many of the possible data hazards.

<span style="font-family: Arial,Helvetica,sans-serif;">** Load instruction issue **
<span style="font-family: Arial,Helvetica,sans-serif; font-size: 11pt; line-height: 115%;">LW instruction does not get the required data until this data is moved to the Data Memory (DM)

<span style="font-family: Arial,Helvetica,sans-serif; font-size: 11pt; line-height: 115%;">part. With the data forwarding mechanism presented above, the best that can be achieved is to

<span style="font-family: Arial,Helvetica,sans-serif; font-size: 11pt; line-height: 115%;">forward the EXE output of one instruction to the EXE input of the next instruction in case of data

<span style="font-family: Arial,Helvetica,sans-serif; font-size: 11pt; line-height: 115%;">dependencies. But if we use the previous mechanism, we cannot solve the data dependency between

<span style="font-family: Arial,Helvetica,sans-serif; font-size: 11pt; line-height: 115%;">a load (LW) instruction and the next instruction since we need the LW output at the EXE input of next

<span style="font-family: Arial,Helvetica,sans-serif; font-size: 11pt; line-height: 115%;">instruction. This happens all in all situations except the case when the next instruction is a store instruction.

<span style="font-family: Arial,Helvetica,sans-serif;">Our solution for this issue is simple and straight-forward: we introduce a bubble in the pipeline.

<span style="font-family: Arial,Helvetica,sans-serif;">The detailed process is as follows:

<span style="font-family: Arial,Helvetica,sans-serif;">1. We decode the instruction in IF stage, so we can know which instruction is LW (load) in IF stage.

<span style="font-family: Arial,Helvetica,sans-serif;">2. If the instruction is a load instruction, we add a bubble, even though we do not know whether there is

<span style="font-family: Arial,Helvetica,sans-serif;">a hazard between this load instruction and the next instruction.

<span style="font-family: Arial,Helvetica,sans-serif;">3. Therefore the pipeline is stalled for one time. As we are going to send a bubble, we do not need to read instruction next time.

<span style="font-family: Arial,Helvetica,sans-serif;">**Milestone 5 - Cache**

<span style="font-family: Arial,Helvetica,sans-serif;"> **Parameter description**

<span style="display: block; font-family: 'Times New Roman',serif; line-height: normal;">

<span style="display: block; font-family: Arial,Helvetica,sans-serif; text-align: center;">
 * Block size || 4*32B ||
 * Associativity || 1 ||
 * Number of blocks in cache || 16 ||
 * Total || 2 KB ||

<span style="font-family: Arial,Helvetica,sans-serif;">**Time sequence**

<span style="font-family: Arial,Helvetica,sans-serif;">As we have to read the memory in case of cache miss, we use a two-tier time sequence. <span style="font-family: Arial,Helvetica,sans-serif;">We use the low frequency clock to control the pipeline and the high frequency one to  <span style="font-family: Arial,Helvetica,sans-serif;">fasten the transmission of data from memory to cache. Thus, we make sure we get the <span style="font-family: Arial,Helvetica,sans-serif;">right data even if there is a conflict miss and the data is not in the cache.

<span style="font-family: Arial,Helvetica,sans-serif; line-height: normal;">**Cache miss** <span style="font-family: Arial,Helvetica,sans-serif; line-height: normal;"> <span style="font-family: Arial,Helvetica,sans-serif;">If data is found in the cache then everything is ok and the fastness of direct mapped cache <span style="font-family: Arial,Helvetica,sans-serif;">is fully exploited (less time to search for data in cache as compared to higher associativity). <span style="font-family: Arial,Helvetica,sans-serif;">The problem arises when the processor tries to read data form cache but the data is not found. <span style="font-family: Arial,Helvetica,sans-serif;">In this case, we fetch the data. In order to do this, we take advantage that there are two edges in one clock cycle. <span style="font-family: Arial,Helvetica,sans-serif;">We use the falling edge to check if it needs to read from memory or write to memory. If so, we read from or write to memory. <span style="font-family: Arial,Helvetica,sans-serif;"> In the rising edge, if we know from the falling edge part we should read or write, we will bring the data from memory to  <span style="font-family: Arial,Helvetica,sans-serif;">cache (in case of a read) or send the data to memory (in case of a write). After completing this process, we set the dirty and valid bits.

<span style="font-family: Arial,Helvetica,sans-serif;">**Write method** <span style="font-family: Arial,Helvetica,sans-serif;">The write method used is write back. Since the cache is large (2KB) compared to data required for the given problem, <span style="font-family: Arial,Helvetica,sans-serif;">there are not many write backs and this method clearly outperforms a write-through method.
 * Results**

Our final results including: –Total Branch Count –Total Miss predicted Branches –Instruction Memory Access Count –Instruction Cache Misses –Data Memory Access Count –Data Cache Misses –Data Cache Write-Backs